The above described copending patent application describes the need for high accuracy variable gain amplification over wide frequency bandwidths. An implementation is described in which a plurality of variable gain amplifier stages are coupled by an attenuation circuit that receives a voltage input to be amplified. A control circuit activates each of the variable gain amplifier stages in a seamless manner in accordance with a control signal applied to a voltage control node, while maintaining no more than one of the stages active at any time. Each amplifier stage should provide variable gain with accurate linearity over that portion of the control voltage range within which it is operable.
A known prior art variable gain amplifier circuit is described, for example, in the publication A Power-Efficient, Low-Distortion Variable Gain Amplifier Consisting of Coupled Differential Pairs, by van Lieshout and van de Plassche, IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, December 1997, and in U.S. Pat. No. 5,742,203 to Van DE Plassche et al. FIG. 1 of the present disclosure illustrates a similar prior art variable gain amplifier. Each stage of a wide dynamic range multi-stage variable gain amplifier may comprise a circuit such as shown in FIG. 1 which, for ease of explanation, is designated with “k” character references, representing amplifier stage K.
The amplifier stage receives an input Vin+, Vin− and provides an output Iout+, Iout−. The inputs are applied to emitter follower transistors 20 and 22, which are coupled to ground through respective current sources. Connected in series between transistor 20 and ground are resistors 24-32, and a current gain control GCk. The gain control may be derived from a variable control voltage setting (not shown) in the manner described, for example, in the above-identified Min application. Connected in series between transistor 22 and ground are resistors 34-42, and gain control GCk.
Connected between Iout+ and Iout− are six differential pairs of transistors. The emitters of a first differential pair of transistors 44 and 66 are connected together. The emitters of a second differential pair of transistors 46 and 64 are connected together. The emitters of a third differential pair of transistors 48 and 62 are connected together. The emitters of a fourth differential pair of transistors 50 and 60 are connected together. The emitters of a fifth differential pair of transistors 52 and 58 are connected together. The emitters of a sixth differential pair of transistors 54 and 56 are connected together. In circuit with each of the transistor emitters is a tail current source.
The base of transistor 44 is connected to the emitter of transistor 20. The base of transistor 48 is connected to the junction between resistors 26 and 28. The base of transistor 50 is connected to the junction between resistors 28 and 30. The base of transistor 52 is connected to the junction between resistors 30 and 32. The base of transistor 54 is connected to the junction between resistor 32 and GCk. The base of transistor 56 is connected to the emitter of transistor 22. The base of transistor 58 is connected to the junction between resistors 34 and 36. The base of transistor 60 is connected to the junction between resistors 36 and 38. The base of transistor 62 is connected to the junction between resistors 38 and 40. The base of transistor 64 is connected to the junction between resistors 40 and 42. The base of transistor 66 is connected to the junction between resistor 42 and GCk.
Transistors 20 and 22 function as a buffer circuit for the voltage input. The emitters of these transistors provide versions of the input signal to the bases of the transistors 44-66 that are shifted in accordance with the voltage drops across resistors 24-42. If the resistances of all resistors are equal (R), an offset voltage exists between the bases of each differential pair of transistors. The offset for the first pair is equal to the difference between the buffered input voltage at the base of transistor 44 and the voltage drops across the five resistors 34 through 42, or proportional to 5×R. The offsets for the second through sixth pairs are proportional to 3×R, R, R, 3×R and 5×R, respectively. The offset for each pair is designated Ri, wherein i represents the number of differential pairs.
With zero gain control currents in the resistor paths, all differential pairs operate without offset and maximum gain is obtained. Increasing the gain control current will produce different offsets across the individual pairs, thereby downwardly adjusting the gain. The gain vs control current is represented by the following relationship:
                                          I            out                    ⁡                      (                          V              in                        )                          ⁢                  α          F                *                  I          ptat                *                              ∑                          i              =              1                        n                    ⁢                      tanh            ⁢                                                            v                  in                                -                                                      R                    i                                    ·                                      GC                    i                                                                              2                ⁢                                  V                  T                                                                                        (        1        )            Where IK is the differential tail current, αF is the ratio between collector and emitter current of the corresponding transistors, VT is the thermal voltage, and Ri, is the resistance offset value for differential pair i. The transconductance can be derived by differentiating Iout with respect to Vin.
                              gm          ⁡                      (                          V              in                        )                          =                                                            α                F                            *                              I                ptat                                                    2              ⁢                              V                T                                              *                                    ∑                              i                =                1                            n                        ⁢                          sec              ⁢                                                          ⁢                              h                2                            ⁢                                                                    V                    in                                    -                                                            R                      i                                        ·                                          GC                      i                                                                                        2                  ⁢                                      V                    T                                                                                                          (        2        )            
The gain vs gain control current GC is plotted in FIG. 2. The linear-in-dB output vs input relationship is not precise. The plot exhibits curvature, the extent of which can be appreciated more clearly in the plot of FIG. 3. Linearity error is plotted over the range of gain control current GC in the diagram of that figure. The gain is relatively linear in the central range, of approximately 0.4 m to 0.6 m, while having increasing error through the range above 0.6 m. A need exists for higher accuracy gain control over the extended range.
The gain control current is normally referenced to a voltage that is temperature-independent. As evident from equation (2), transconductance is a function of thermal voltage VT, which varies with temperature. VT is an element in the denominator of two portions of the gain equation. Thus, in the known amplifier gain stage of FIG. 1, gain is variable with temperature. A need exists to compensate for such variability so that the amplifier gain is independent of temperature.